This comprehensive two part course is a thorough introduction to the VHDL language using Vivado Design Suite. The emphasis during the first three days is on writing solid synthesizable code and enough simulation code to write a viable testbench. and techniques aimed at creating parameterizable and reusable designs. Structural, register transfer level (RTL), and behavioral coding styles are covered. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. In this five-day course, you will gain valuable hands-on experience.
Incoming students with little or no VHDL knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations.
During the second stage of this course, Increase your VHDL proficiency by learning advanced techniques that will help you write more robust and reusable code. This comprehensive course is targeted toward designers who already have some experience with VHDL.
The course highlights modeling, testbenches, RTL/synthesizable design, and techniques aimed at creating parameterizable and reusable designs. The majority of class time is spent in challenging hands-on labs as compared to lecture modules.